Volume 17 • Issue 2 • PP: 426-435 • 2025
Neuromorphic VLSI Accelerator for Edge-Aware AI Processing Using Hybrid Spiking Neural Architectures
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© 2025 The Author(s). Published by ASPG. This article is licensed under the Creative Commons Attribution 4.0 International License (CC BY 4.0).
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The rapid proliferation of edge-AI systems in IoT, autonomous robotics, and biomedical monitoring demands ultra-low-power, latency-aware intelligence that conventional deep neural networks struggle to provide due to heavy computation and memory overheads. Neuromorphic computing offers a promising biological-inspired alternative by processing information through sparse spiking events, enabling energy-efficient on-device learning and inference. This paper presents a neuromorphic VLSI accelerator based on a hybrid spiking neural architecture that combines Leaky-Integrate-and-Fire (LIF) neurons, adaptive threshold spiking units, and synaptic plasticity circuits to support both supervised and unsupervised learning modes at the edge. A hierarchical crossbar-memory topology integrated with non-volatile memristive synapses provides dense weight storage and real-time synaptic updates, reducing off-chip memory access by 78%. A pipelined event-driven computation engine and clock-gated spike scheduler minimize dynamic switching, achieving 61% reduction in power and 2.4× throughput improvement compared to conventional CMOS DNN accelerators. The proposed system performs dynamic visual-feature encoding, spike-based temporal fusion, and on-chip learning for anomaly and object detection tasks in low-power sensor nodes. Fabricated in 28-nm CMOS, the prototype achieves 0.29 mW power, 0.42 pJ/spike energy, and 94.3% inference accuracy, outperforming state-of-the-art neuromorphic platforms. Results demonstrate that hybrid spiking architectures integrated with VLSI-efficient plasticity circuits can deliver high-accuracy, self-adaptive AI within stringent edge constraints, enabling next-generation smart-sensing and autonomous micro-robotic intelligence.
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