Volume 9 , Issue 1 , PP: 18-33, 2025 | Cite this article as | XML | Html | PDF | Full Length Article
Tamilselvan A. 1 * , Devika T. 2 , Anitha S. 3
Doi: https://doi.org/10.54216/IJWAC.090102
This work investigates into the meticulous analysis of the Transmission Gate (TG) based D Flip-Flop integrated with dynamic XOR-based clock gating, aimed at analyzing power consumption patterns and potential power savings across varying frequencies. While power consumption inherently reduces with smaller technology nodes, but this work demonstrates that dynamic clock gating can achieve further power savings, especially at higher operational frequencies and lower data activity. The outcomes represent a deeper understanding of power optimization techniques for sequential circuits. The analysis is performed using Cadence Virtuoso in a 90nm technology process, which determine the sophisticated interaction between design elements and power dynamics. Through comprehensive simulations, the power consumption of TG-based D flip-flops is meticulously examined across diverse technology nodes. Furthermore, the efficacy of integrating dynamic XOR-based clock gating to this flip-flop design is explored, unveiling its potential to yield substantial power savings. The research underscores the multifaceted nature of low-power design strategies, emphasizing their relevance across various hierarchies including system, architecture, circuit, and device levels. While advancements in technology nodes naturally lead to reduced power dissipation, this study illuminates the additional power-saving opportunities presented by the dynamic XOR-based clock gating approach. Especially, in this investigation highlights the significance of this approach particularly in scenarios characterized by higher frequencies of operation and low data activity. By leveraging dynamic XOR-based clock gating, the research showcases how power efficiency can be further augmented, offering insights into enhancing the overall energy efficiency of digital systems. In summary, this project provides a nuanced understanding of power dynamics in TG-based D flip-flops, shedding light on the intricate balance between technology advancements and innovative design methodologies for achieving optimal power efficiency. Through meticulous analysis and simulation, it unveils a promising avenue for realizing significant power savings, thereby contributing to the advancement of low-power design paradigms in modern digital systems.
TG-based D Flip-Flop , Dynamic XOR-based Clock Gating , Power Consumption , 90nm Technology , Cadence Virtuoso , Low-power Design and Technology Nodes.
[1] E. Lee and Y. Kim, "A Power-Efficient 10T D Flip-Flop with Dual Line of Four Switches using 65nm CMOS Technology," 2023 20th International SoC Design Conference (ISOCC), Jeju, Korea, Republic of, 2023, pp. 315-316, doi: 10.1109/ISOCC59558.2023.10396628
[2] M. Voernes, T. Ytterdal and S. Aunet, "Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout," 2014 NORCHIP, Tampere, Finland, 2014, pp. 1-6, doi: 10.1109/NORCHIP.2014.7004746.
[3] T. Chindhu S. and N. Shanmugasundaram, "Clock Gating Techniques: An Overview," 2018 Conference on Emerging Devices and Smart Systems (ICEDSS), Tiruchengode, India, 2018, pp. 217-221, doi: 10.1109/ICEDSS.2018.8544281.
[4] Himanshu Chaudhary, Nithish Goyal, Nagendra Sah “Dynamic Power Reduction Using Clock Gating: A Review” IJECT
[5] G. S. R. Srivatsava, P. Singh, S. Gaggar and S. K. Vishvakarma, "Dynamic power reduction through clock gating technique for low power memory applications," 2015 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT), Coimbatore, India, 2015, pp. 1-6, doi: 10.1109/ICECCT.2015.7226204.
[6] Jinn-Shyan Wang and Po-Hui Yang, "A pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications," 1998 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 1998, pp. 93-96 vol.2, doi: 10.1109/ISCAS.1998.706849.
[7] V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel and F. Baez, "Reducing power in high-performance microprocessors," Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), San Francisco, CA, USA, 1998, pp. 732-737, doi: 10.1145/277044.277227.
[8] M. Aguirre-Hernandez and M. Linares-Aranda, "A Clock-Gated Pulse-Triggered D Flip-Flop for Low-Power High-Performance VLSI Synchronous Systems," 2006 International Caribbean Conference on Devices, Circuits and Systems, Playa del Carmen, Mexico, 2006, pp. 293-297, doi: 10.1109/ICCDCS.2006.250876.
[9] P. Zhao and Z. Wang, "Low power design of vlsi circuits and systems," 2009 IEEE 8th International Conference on ASIC, Changsha, China, 2009, pp. 17-20, doi: 10.1109/ASICON.2009.5351616.
[10] M. Maiti, A. Paul, S. K. Saw and A. Majumder, "A Dynamic Current Mode D-Flipflop for High Speed Application," 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), Kolkata, India, 2019, pp. 1-3, doi: 10.1109/IEMENTech48150.2019.8981081.
[11] P. Parekh, F. Yuan and Y. Zhou, "Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability," 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA, 2020, pp. 182-185, doi: 10.1109/MWSCAS48704.2020.9184567.
[12] E. Låte, A. A. Vatanjou, T. Ytterdal and S. Aunet, "Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI," 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), Oslo, Norway, 2015, pp. 1-4, doi: 10.1109/NORCHIP.2015.7364372.
[13] S. Panda, S. Sharma and A. R. Asati, "Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes," 2020 IEEE 7th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), Prayagraj, India, 2020, pp. 1-6, doi: 10.1109/UPCON50219.2020.9376565.
[14] R. N. Agnes Shiny, B. Fahimunnisha, S. Akilandeswari and S. J. Venula, "Integration of Clock Gating and Power Gating in Digital Circuits," 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS), Coimbatore, India, 2019, pp. 704-707, doi: 10.1109/ICACCS.2019.8728370.
[15] P. Sahu and S. K. Agrahari, "Comparative Analysis of Different Clock Gating Techniques," 2020 5th IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE), Jaipur, India, 2020, pp. 1-6, doi: 10.1109/ICRAIE51050.2020.9358375.
[16] B. Thiyaneswaran, S. Kumarganesh, M.Dharmalingam, P N Palanisamy, L.Vasanth, A. Immanuvel “Environmental Pollution and Weather Data Monitoring Using Lora Low Power VLSI solution” Ninth International Conference on Science Technology Engineering and Mathematics (ICONSTEM), 4th & 5th April 2024, doi: 10.1109/ICONSTEM60960.2024.10568664..
[17] K. Baskar, K. Muthumanickam, P. Vijayalakshmi & S. Kumarganesh, (2024), “A Strong Password Manager Using Multiple Encryption Techniques”. Journal of The Institution of Engineers (India): Series B, pp. 1-8, DOI: https://doi.org/10.1007/s40031-024-01144-6
[18] S. Kumarganesh, S. Anthoniraj, T.Senthil Kumar, P.Elayaraja, et al. (2022), “A Novel Analytical Framework is Developed for Wireless Heterogeneous Networks for Video Streaming Applications” Journal of Mathematics, 2022(1) pp.1-7 doi:https://doi.org/10.1155/2022/2100883
