Volume 9 , Issue 1 , PP: 01-17, 2025 | Cite this article as | XML | Html | PDF | Full Length Article
Kumarganesh S. 1 * , Socratees P. 2 , Rajamanickam G. 3
Doi: https://doi.org/10.54216/IJWAC.090101
A common symmetric key block cypher for protecting electronic data is called the Advanced Encryption Standard (AES). The implementation of the AES algorithm using Very-Large-Scale Integration (VLSI) is examined in this study. Cryptographic algorithms can be realised in hardware thanks to VLSI, which has advantages over software implementations in terms of increased processing speed and security. In this work, an AES block cypher core designed and implemented with VLSI techniques is described. We investigate various architectural designs to maximise performance indicators such as area, power consumption, and throughput. The trade-offs between different implementation options and design concerns for important components such as S-boxes will be covered. To illustrate the performance and usefulness of the implemented AES core, simulation results will be given. This paper examines the VLSI implementation of the Advanced Encryption Standard (AES), with a focus on image processing applications, even though it is essential for general data security. Effective on-chip encryption and decryption can be included into image processing systems by implementing the AES algorithm into specialised hardware circuits. Benefits of this VLSI design include enhanced performance over software-based solutions on resource-constrained image processing devices, the ability to encrypt images in real-time for secure transmission or storage, and the potential for reduced power usage for battery-powered applications.
Advanced Encryption Standard (AES) , Very-Large-Scale Integration (VLSI) Algorithm , Block cipher , Data hiding , S-boxes
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