Volume 5 , Issue 1 , PP: 44-53, 2022 | Cite this article as | XML | Html | PDF | Full Length Article
Pushan K. Dutta 1 * , David Winters 2 , Nader Behdad 3 , Mohamed Saber 4
Doi: https://doi.org/10.54216/IJWAC.050104
A proposed design and FPGA implementation of a demodulator and phase compensation system is presented. The system is simple, accurate, dissipate low power. Simulations indicate that the proposed system compensates the error in the received phase quickly which decreases the bit error rate (BER) in wireless systems. FPGA implementation of the proposed system shows a power reduction by 27.91% and the speed by 66.89% compared to Costas loop.
Phase shift keying , Phase Compensation , Phase locked loop , Costas loop , Field programmable gate array
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