International Journal of Wireless and Ad Hoc Communication IJWAC 2692-4056 10.54216/IJWAC https://www.americaspg.com/journals/show/1346 2019 2019 Artificial Intelligence and Robotics, School of Engineering and Technology, Amity University Kolkata,India Pushan Pushan Computer Science and Engineering, Shivalik Group of Collegers, Dehradun, 248001, David Winters Electrical and Computer Engineering , The Polytechnic University of the Philippines, Manila, 1016, Philippines Nader Behdad Dep. of Electronics and Communication Engineeinrg, Faculty of Engineering Delta University for Science and Technology, Gamssa City, Mansoura, Egypt Mohamed Saber A proposed design and FPGA implementation of a demodulator and phase compensation system is presented. The system is simple, accurate, dissipate low power. Simulations indicate that the proposed system compensates the error in the received phase quickly which decreases the bit error rate (BER) in wireless systems. FPGA implementation of the proposed system shows a power reduction by 27.91% and the speed by 66.89% compared to Costas loop. 2022 2022 44 53 10.54216/IJWAC.050104 https://www.americaspg.com/articleinfo/20/show/1346