Volume 9 , Issue 2 , PP: 01-11, 2025 | Cite this article as | XML | Html | PDF | Full Length Article
Chandraman M. 1 * , Chandraman M. 2 * , Santhiyakumari N. 3 , Saravanan V. 4 , Shanmugasundaram P. 5 , Arun A. 6
Doi: https://doi.org/10.54216/IJWAC.090201
Artificial intelligence (AI) is becoming more and more necessary for devices, particularly for network edge image processing applications. Building Very-Large-Scale Integration (VLSI) systems that are specifically tuned for low power consumption and enable edge AI techniques for real-time image processing is the aim of this research. One of Edge AI's key characteristics is its ability to process data and make judgements instantly. Edge AI reduces latency by eliminating the need to move massive amounts of data from one location to the cloud. Quick response times are made feasible, which is essential for applications such as industrial automation and autonomous driving. The study will investigate hardware accelerators and approximation computing as efficient approaches to perform image processing algorithms on low-resource edge devices. If all created data were transferred to the cloud, the network infrastructures would be overwhelmed by the exponential growth in linked devices. Edge AI solves this issue by significantly reducing the amount of data that needs to be sent across the network by doing computations locally. This increases the scalability of AI systems and decreases operating costs associated with data transport. By using custom VLSI design, the project aims to achieve significant energy savings over traditional software-based solutions. This will pave the way for edge AI to be widely applied in battery-powered devices for longer battery life and tasks like object and picture identification.
Edge AI , Artificial Intelligence , Very-Large-Scale Integration (VLSI) Algorithm , Energy Consumption , Edge Detection
[1] Z. Y. Wong, D. C. K. Wong, W. K. Lee, and K. M. Mok, "High-Speed RLWE-Oriented Polynomial Multiplier Utilizing Karatsuba Algorithm," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 6, pp. 2157–2161, Jun. 2021, doi: 10.1109/TCSII.2020.3049002.
[2] Y. D. Chih et al., "13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference," in 2020 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2020, pp. 222–224, doi: 10.1109/ISSCC19947.2020.9062955.
[3] T. Li, Y. Ma, K. Yoshikawa, and T. Endoh, "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 7, pp. 1078–1082, Jul. 2023, doi: 10.1109/TVLSI.2023.3245099.
[4] Y. Wang, J. Lin, and Z. Wang, "An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 2, pp. 280–293, Feb. 2018, doi: 10.1109/TVLSI.2017.2767624.
[5] H. Waris, C. Wang, W. Liu, and F. Lombardi, "AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 5, pp. 1566–1570, May 2021, doi: 10.1109/TCSII.2021.3065333.
[6] M. Vanitha, R. Sakthivel, and Subha, "Highly secured high throughput VLSI architecture for AES algorithm," in 2012 International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, India, 2012, pp. 403–407, doi: 10.1109/ICDCSyst.2012.6188751.
[7] K. Shahbazi and S. B. Ko, "Area-Efficient Nano-AES Implementation for Internet-of-Things Devices," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 1, pp. 136–148, Jan. 2021, doi: 10.1109/TVLSI.2020.3033928.
[8] G. Ramtri and C. Patel, "Secure Banking Transactions Using RSA and Two Fish Algorithms," in 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE), Vellore, India, 2020, pp. 1–5, doi: 10.1109/ic-ETITE47903.2020.236.
[9] D. Smekal, J. Hajny, and Z. Martinasek, "Hardware-Accelerated Twofish Core for FPGA," in 2018 41st International Conference on Telecommunications and Signal Processing (TSP), Athens, Greece, 2018, pp. 1–5, doi: 10.1109/TSP.2018.8441386.
[10] V. R. Kavuri and A. T. P., "Efficient Secured Cloud Storage System using Dynamic Multiple Clouds Cryptographic Algorithm," in 2023 7th International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC), Kirtipur, Nepal, 2023, pp. 399–405, doi: 10.1109/I-SMAC58438.2023.10290155.
[11] J. Zhao, "DES-Co-RSA: A Hybrid Encryption Algorithm Based on DES and RSA," in 2023 IEEE 3rd International Conference on Power, Electronics and Computer Applications (ICPECA), Shenyang, China, 2023, pp. 846–850, doi: 10.1109/ICPECA56706.2023.10075771.
[12] D. V. Rao, S. P. K. Reddy, C. Anusha, D. Bhoomika, and R. Venkateswarlu, "Image Security is Improved by Super Encryption using RSA and Chaos Algorithms," in 2023 Second International Conference on Electronics and Renewable Systems (ICEARS), Tuticorin, India, 2023, pp. 1–5, doi: 10.1109/ICEARS56392.2023.10085142.
[13] P. Parvathy and A. S. R. Ajai, "VLSI Implementation of Blowfish Algorithm for Secure Image Data Transmission," in 2020 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2020, pp. 770–774, doi: 10.1109/ICCSP48568.2020.9182088.
[14] Y. Qingmin and W. Sinan, "Signature system based on RSA algorithm and its algorithm optimization," in 2021 IEEE Conference on Telecommunications, Optics and Computer Science (TOCS), Shenyang, China, 2021, pp. 703–706, doi: 10.1109/TOCS53301.2021.9688864.
[15] B. V. Prakash, A. Rajiv Kannan, N. Santhiyakumari, S. Kumarganesh, et al., "Meningioma brain tumor detection and classification using hybrid CNN method and RIDGELET transform," Scientific Reports, vol. 13, no. 14522, pp. 1–13, 2023, doi: 10.1038/s41598-023-41576-6.
[16] J. Kim, H. Lee, and Y. Park, "Low-Power and High-Performance Hardware Implementation of AES Algorithm for Secure Communications," IEEE Access, vol. 11, pp. 55523–55535, 2023, doi: 10.1109/ACCESS.2023.3274511.
[17] S. Kumarganesh, M. Murugesan, C. Ganesh, N. Santhiyakumari, M. Thangavel, et al., "Hybrid Plasmonic Biosensors with Deep Learning for Colorectal Cancer Detection," Plasmonics Journal, pp. 1–15, 2024, doi: 10.1007/s11468-024-02568-y.
