[1] B. Sklar, F. Harris, Digital Communications: Fundamentals and Applications, 3rd edition, Pearson, 2020.

[2] Fuyun Ling, Synchronization in Digital Communication Systems 1st Edition, Cambridge university press,

2017.

[3] V. Bagad, Wireless Communication. Technical Publications, 2009.

[4] Thomas Paul Weldon, Analog and Digital Communication Lecture Notes,

[5] B. lathi, Z. Ding, Modern Digital and Analog Communication, 5th edition, Oxford university press, 2018.

[6] H. Xiao, X. Liu and L. Zhou, Design of PCM/FM Baseband Modulation Transmitter Based on Software

Radio, 2018 Eighth International Conference on Instrumentation & Measurement, Computer,

Communication and Control (IMCCC), 714-717, 2018.

[7] X. Huang, Research on variable rate PCM/FM telemetry modulation and demodulation technology, 2016

IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB), 1-5, 2016.

[8] Z. Wan, W. Rhee and Z. Wang, "A Nonlinearity-Calibration-Free Reconfigurable ADPLL for General

Purpose Frequency Modulation," 2020 IEEE International Conference on Integrated Circuits, Technologies

and Applications (ICTA), 19-20, 2020.

[9] S. Wenyou and H. Yonghong, "Design and Realization of Direct PLL FM Transmitter for UAV Data

Link," 2009 WASE International Conference on Information Engineering, 522-525, 2099.

[10] S. J. A. Bakar, S. Setumin and A. I. C. Ani, "PLL System with Active PI Filter for FM Demodulation

Application," 2022 IEEE 13th Control and System Graduate Research Colloquium (ICSGRC),151-154,

2022.

[11] B. Schlecker, M. Dukic, B. Erickson, M. Ortmanns, G. Fantner and J. Anders, Single-Cycle-PLL Detection

for Real-Time FM-AFM Applications, in IEEE Transactions on Biomedical Circuits and Systems, vol. 8(2),

206-215, 2014.

[12] J. Lee, Y. Baek, I. Eo and B. Koo, A Ka-Band FMCW PLL Synthesizer with 8.5-GHz Bandwidth for High-

Precision High-Resolution Sub-mmWave Radar Sensing, 2021 IEEE International Symposium on Circuits

and Systems (ISCAS), 1-5, 2021.

[13] Salamai, Abdullah Ali, El-Sayed M. El-kenawy, and Ibrahim Abdelhameed. "Dynamic voting classifier for

risk identification in supply chain 4.0." CMC-COMPUTERS MATERIALS & CONTINUA 69, no. 3 (2021):

3749-3766.

[14] Forouhar Farzaneh; Ali Fotowat; Mahmoud Kamarei; Ali Nikoofard; Mohammad Elmi, 3 PLL, FM

Modulation, and FM Demodulation, in Introduction to Wireless Communication Circuits, River Publishers,

125-168, 2020.

[15] A. S. Prabhu and V. Elakya, Design of modified low power booth multiplier, 2012 International Conference

on Computing, Communication and Applications, 1-6, 2012.

[16] D. Govekar and A. Amonkar, Design and implementation of high speed modified booth multiplier using

hybrid adder, 2017 International Conference on Computing Methodologies and Communication (ICCMC),

138-143, 2017.

[17] Eid, Marwa M., El-Sayed M. El-kenawy, and Abdelhameed Ibrahim. "A binary sine cosine-modified whale

optimization algorithm for feature selection." In 2021 National Computing Colleges Conference (NCCC), pp.

1-6. IEEE, 2021.

[18] D. Kalaiyarasi and M. Saraswathi, Design of an Efficient High Speed Radix-4 Booth Multiplier for both

Signed and Unsigned Numbers, 2018 Fourth International Conference on Advances in Electrical, Electronics,

Information, Communication and Bio-Informatics (AEEICB), 1-6, 2018.

[19] G. P. Ao, The Basic Principle and FPGA Implementation of NCO, 2012 Second International Conference on

Instrumentation, Measurement, Computer, Communication and Control, 90-94, 2012.

[20] El-kenawy, El-Sayed M., Hattan F. Abutarboush, Ali Wagdy Mohamed, and Abdelhameed Ibrahim.

"Advance artificial intelligence technique for designing double T-shaped monopole antenna." CMCCOMPUTERS

MATERIALS & CONTINUA 69, no. 3 (2021): 2983-2995.

[21] S. Hu, H. Li and J. Huang, An Optimal Algorithm for Designing NCO Circuit in Mobile Communication

Systems," 2009 WRI International Conference on Communications and Mobile Computing, 372-376, 2009.

[22] L. Zhihua and W. Weilian, "The design of NCO based on CORDIC algorithm and implementation in

FPGA(∗)," 2011 International Conference on Electronics, Communications and Control (ICECC), 2902-

2905, 2011.

[23] M. Asif and Z. Ahmed, "Design of Optimized NCO for FSK Modem," 2005 Student Conference on

Engineering Sciences and Technology, 1-4, 2005.

[24] M. Saber, Y. Jitsumatsu, Y. M.T.A. Khan, A Simple Design to Mitigate Problems of Conventional Digital

Phase Locked Loop, Signal Processing: An international journal (SPIJ), vol.6 (2),65-77, 2012.

[25] J. Guojun and S. Wenzhong, "Stability of bilinear time-delay systems," in IMA Journal of Mathematical

Control and Information, vol. 18(1) 53-60, 2001.

[26] Zhang Tingting et al., "An s-z domain transformation method for the readout circuit design of closed-loop

micromechanical capacitive accelerometer," 2012 IEEE International Conference on Electron Devices and

Solid State Circuit (EDSSC), 1-3, 2012.

[27] M. Saber and Y. Jitsumatsu and M. T. A. Khan, Low Noise-Low Power Digital Phase-Locked Loop, IEEE

Region 10 Conference (TENCON) 2010, 1324-1329, Nov. 2010.

[28] M. Saber, Y. Jitsumatsu and M. T. A. Khan, Design and Implementation of Low Power Digital Phase -

Locked Loop, in Proc. of 2010 Int. Sympo. on Spread Spectrum Techniques and Applications, 928-933,

2010.

[29] Mohamed Saber, Efficient Phase Recovery System, Indonesian Journal of Electrical Engineering and

Computer Science, vol.5 (1), 123-129, 2017.

[30] Mohamed Saber, A novel design and Implementation of FBMC transceiver for low power applications,

Indonesian Journal of Electrical Engineering and Informatics, vol. 8(1), 83-93, 2020.

[31] R. Das, A. Guha and A. Bhattacharya, "FPGA based higher order FIR filter using XILINX system

generator," 2016 International Conference on Signal Processing, Communication, Power and Embedded

System (SCOPES), 111-115, 2016.

[32] Z. J. Xiang, L. Wang, Y. Jiang, D. Liu and J. Wang, "A Framework for Xilinx SRAM-based FPGA

Functional Test," 2020 IEEE 3rd International Conference on Electronics and Communication Engineering

(ICECE), 207-210, 2020.

[33] P. Priya and S. Ashok, "IIR Digital Filter Design Using Xilinx System Generator for FPGA

Implementation," 2018 International Conference on Communication and Signal Processing (ICCSP), 0054-

0057, 2018.