International Journal of Wireless and Ad Hoc Communication IJWAC 2692-4056 10.54216/IJWAC https://www.americaspg.com/journals/show/3741 2019 2019 Associate Professor, Department of ECE, Knowledge Institute of Technology, Salem, Tamil Nadu, India Saravanan Saravanan Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem, Tamil Nadu, India Elarmathi. S. PG Scholar, Department of ECE, Knowledge Institute of Technology, Salem, Tamil Nadu, India Rajalakshmi V.. R. A recent study examined the applications of multiplication and division in video and image manipulation and there has been mention of machine learning. DSP blocks that function as high performance multipliers are given by FPGA providers. However routing lag time and inefficiencies, particularly for lower bit width multiplications, might emerge from the fixed placements and restricted number of these FPGA multipliers, raising power consumption. FPGA companies offer IP cores that are soft made especially for multiplication to solve this problem. Even if these IP cores have improved over time, they can yet be improved. This can be accomplished by creating low latency, accurate, and core multiplier topologies that maximize the space of FPGA and take advantage of its architectural characteristics, like rapid carry chains and look up table structures.  These architectures seek to improve overall efficiency by lowering the crucial path delay and multiplier resource consumption. Here a proposed method for building accurate and approximate signed and unsigned multipliers for an eight bit configuration is presented. This entails changing the LUT 6 architecture to use a one LUT 5 with multiplexers in place of a dual LUT 5 with multiplexers. Using Xilinx software, the design was built in Verilog HDL and synthesized. At the conclusion of the process, variables including area, delay and power were compared. 2025 2025 12 23 10.54216/IJWAC.090202 https://www.americaspg.com/articleinfo/20/show/3741