aspg-20-1347-1791307691 20261006172811 American Scientific Publishing Group admin@americaspg.com American Scientific Publishing Group International Journal of Wireless and Ad Hoc Communication IJWAC 2692-4056 2022 4 2 Khadija Shazly Faculty of Computer and Information, Mansoura university, Egypt Mohamed E. Ghoneim Department of Mathematical Sciences, Faculty of Applied Science, Umm Al-Qura University, 21955 Makkah, Saudi Arabia Sunil Kumar School of Computer Science, University of Petroleum and Energy Studies, Dehradun, 248001, India In this paper, we introduce the design of a digital frequency modulation receiver using FPGA. The main component in the design is digital phase locked loop (DPLL) which compensate any changes between the frequency and phase of the input modulated signal and the frequency and phase of numerically controlled oscillator. The input to the receiver is 8-bit represents the sampled discrete time signal from the analog modulated received frequency modulation signal. The receiver is designed using Xilinx system generator and implemented on the FPGA board (Xilinx Vitrex-7 XC7VX550t board), works with 350 MHz and consumes 120 mW. 2022 107 116 1347 https://creativecommons.org/licenses/by/4.0/ 10.54216/IJWAC.040206 https://americaspg.com/journal/20/article/1347 https://americaspg.com/storage/9644.pdf