aspg-20-1346-1791307636 20261006172716 American Scientific Publishing Group admin@americaspg.com American Scientific Publishing Group International Journal of Wireless and Ad Hoc Communication IJWAC 2692-4056 2022 5 1 Pushan K. Dutta Artificial Intelligence and Robotics, School of Engineering and Technology, Amity University Kolkata,India David Winters Computer Science and Engineering, Shivalik Group of Collegers, Dehradun, 248001, Nader Behdad Electrical and Computer Engineering , The Polytechnic University of the Philippines, Manila, 1016, Philippines Mohamed Saber Dep. of Electronics and Communication Engineeinrg, Faculty of Engineering Delta University for Science and Technology, Gamssa City, Mansoura, Egypt A proposed design and FPGA implementation of a demodulator and phase compensation system is presented. The system is simple, accurate, dissipate low power. Simulations indicate that the proposed system compensates the error in the received phase quickly which decreases the bit error rate (BER) in wireless systems. FPGA implementation of the proposed system shows a power reduction by 27.91% and the speed by 66.89% compared to Costas loop. 2022 44 53 1346 https://creativecommons.org/licenses/by/4.0/ 10.54216/IJWAC.050104 https://americaspg.com/journal/20/article/1346 https://americaspg.com/storage/8642.pdf